SERVICES & TURN-KEY SOLUTIONS PRODUCTS OPEN-SOURCE SOFTWARE PATENTS & PUBLICATIONS CONTACT
ChipDesign offers following services & turn-key solutions:
ChipDesign offers front-to-back mixed-signal / RFIC design services in triple-well bulk and twin-well PD- and FD-SOI/SOS CMOS processes (interested in FinFET), covering IC specification, design, layout, functional verification, packaging and characterization. In addition, ChipDesign also provides antenna and antenna array, IC package (BGA/LGA, DVN/QFN, SOT, WLCSP), capacitive and piezoelectric MEMS device (accelerometers, gyroscopes, inertial measurement units, microphones, resonators, switches), and MMIC (power amplifiers based on III-V compound semiconductors such as GaAs, GaN, and InP) design services, as well as electronic design automation services. ChipDesign has access to state-of-the-art technologies (through MOSIS) and EDA tools (through Cadence).
- IC specification: performance versus power trade-off and partitioning across building blocks (Mathworks MATLAB & Simulink, Verilog-AMS)
- IC design:
- Analog/RF: passive (antenna matching tuner, attenuator, (TTD) phase shifter, SPNT switch, transformer) and active (image-reject mixer, multiplier, LNA, PA, VCO) design. Analysis of non-linear circuits (HB, and (Q)PSS solvers) (Agilent GoldenGate, Cadence Spectre/RF, interested in Mentor Graphics Eldo and Synopsys HSPICE).
- Digital: design (Verilog, VHDL) and synthesis (Cadence RTL Compiler, interested in Mentor Graphics ModelSim and Synopsys Design Compiler). Interested in integration of CPU (ARM Cortex-A), DSP (CEVA), GPU (Imagination), MCU (ARM Cortex-M), and serial I/O interface IP cores (DigRF, RFFE, SPMI) in ASICs (Cadence SoC Encounter).
- EM: differential equation methods (FDTD, FEM), integral equation methods (TDIE, MoM/MLFMM). Interested in domain decomposition methods.
- Mixed-signal: DAC (charge sharing, current steering), DDS, and PLL (PFD/CP, programmable divider, sigma/delta modulator) design. Interested in ADC and ADPLL design (BDA AFS, Cadence UltraSim).
- Power management: AC-DC (voltage multiplier) and DC-DC (buck, boost, Dickson charge pump) converters, linear regulators (LDO, series), and voltage references (band gap).
- IC layout verification using DRC/LVS, parasitic extraction (Cadence Assura, Mentor Graphics Calibre), and EM simulation (Agilent Momentum, Ansys HFSS, CST Microwave Studio, Integrand EMX, Sonnet). IC yield optimization using foundry-supplied PCM data-based Monte Carlo and process corners simulation of extracted views.
- RF IC floor planning (ESD protection, micro-bumps / pad ring, RF grounding), RF IC packaging (DVN/QFN, WLCSP) and signal integrity analysis of PCB designs.
- Mixed-signal ASIC functional verification using Verilog-AMS and digital ASIC/FPGA functional verification using SystemVerilog and UVM (Cadence Incisive).
- On-wafer ASIC characterization, incl. large-signal S-parameter, noise (NF, phase noise), and non-linear measurements (ACPR, CSO, CTB, IP3, P1dB, XMOD). ASIC debugging (FIB).
- III-V compound (D/E-mode GaAs pHEMT) and silicon-based (SiGe:C HBT) semiconductor device and process simulation (Silvaco TCAD), device modeling
(Agilent IC-CAP, Verilog-A). Interested in GaN HEMT, InSb DHBT, and RF CMOS technology.
- Antenna design and integration
- Electronic design automation using Agilent AEL, Ansys VBScript, Cadence OCEAN, Python, ROD and SKILL, and Tcl.
- MEMS design, device modeling and integration
ChipDesign also offers turn-key RF solutions to customers. Examples include:
- Antennas and antenna arrays
- FPGA design
- Packaged MMICs
- PCB design
- PDK development
- Power amplifiers: class A through S PAs based on GaN or LDMOS transistors, incl. tunable matching networks for optimal load-pulling
- SSPA transmitters: two-way and three-way Doherty, EER (Kahn), ET, linear (feedback, feedforward, and predistortion), and outphasing SSPA transmitters